45#define RT_G_INIT_ZERO { 0, BU_LIST_INIT_ZERO, RT_WDB_INIT_ZERO }
50RT_EXPORT
extern struct rt_g RTG;
60#define RT_GET_VLIST(p) BV_GET_VLIST(&RTG.rtg_vlfree, p)
63#define RT_FREE_VLIST(hd) BV_FREE_VLIST(&RTG.rtg_vlfree, hd)
65#define RT_ADD_VLIST(hd, pnt, draw) BV_ADD_VLIST(&RTG.rtg_vlfree, hd, pnt, draw)
68#define RT_VLIST_SET_DISP_MAT(_dest_hd, _ref_pt) BV_VLIST_SET_DISP_MAT(&RTG.rtg_vlfree, _dest_hd, _ref_pt)
71#define RT_VLIST_SET_MODEL_MAT(_dest_hd) BV_VLIST_SET_MODEL_MAT(&RTG.rtg_vlfree, _dest_hd)
74#define RT_VLIST_SET_POINT_SIZE(hd, size) BV_VLIST_SET_POINT_SIZE(&RTG.rtg_vlfree, hd, size)
77#define RT_VLIST_SET_LINE_WIDTH(hd, width) BV_VLIST_SET_LINE_WIDTH(&RTG.rtg_vlfree, hd, width)
Header file for the BRL-CAD common definitions.
struct rt_wdb rtg_headwdb
head of database object list
int8_t rtg_parallel
!0 = trying to use multi CPUs
struct bu_list rtg_vlfree
head of bv_vlist freelist
fundamental vector, matrix, quaternion math macros